Semiconductor electronic components such as LSI (Large-Scale Integrated circuit) mounted on electronic circuit boards have undergone advancements in terms of higher signal speed and lower power supply voltage. This means that power supply noise has an influence upon stable operation and quality of the electronic circuit. Specifically, the suppression of power supply noise, referred to as “power integrity (PI)” is essential in the design of an electronic circuit.
In the design phase of an electronic circuit board (referred to also as a “printed board” or “printed circuit board” below), various proposals have been made heretofore with regard to methods of suppressing and analyzing power supply noise.
For example, Patent Document 1 discloses a method of evaluating the characteristics of a printed circuit board wherein whether design of a printed circuit board that suppresses variations in power supply voltage and prevents an unwanted electromagnetic emission due to resonance of the power supply circuitry could be achieved is evaluated, during or after creation of a board layout prior to manufacturing of the board. The method includes the steps of:
calculating the impedance characteristic of the power supply circuitry within the board as seen from the power supply-terminal connection position of each active element mounted on the printed circuit board;
calculating the impedance characteristic from the power supply-terminal connection position to a capacitor element connected at a position nearest to this connection position; and
determining whether resonance will occur within the power supply circuitry by comparing any among the sizes, phases, real parts or imaginary parts of the impedance characteristic of the power supply circuitry and of the impedance characteristic up to the capacitor element. This method extracts impedance from power supply-to-ground design information, calculates resonance of the board and evaluates the validity of the design. However, it does not analyze power supply noise taking the characteristic of a LSI-chip into consideration. That is, the method does not analyze power supply noise that propagates along the printed circuit board from the LSI chip.
Patent Document 2 discloses a power supply noise analysis method as a method that takes into account power supply noise that propagates along a printed circuit board from an LSI chip. This method makes it possible to analyze power supply noise within a semiconductor integrated circuit taking the effect of a printed board into account and to analyze power supply noise on the printed board generated by the semiconductor integrated circuit. This method includes the steps of:
dividing the semiconductor integrated circuit into a plurality of first unit areas;
expressing a power line, circuit and circuit current consumption of each first unit area by a simplified power supply network, capacitance and current source;
obtaining a model of the overall semiconductor integrated circuit by compiling the power supply networks, capacitances and current sources with regard to the plurality of first unit areas; dividing the printed board on which the semiconductor integrated circuit is mounted into a plurality of second unit areas;
expressing the power supply layer of each second unit area by a power supply network and capacitance;
obtaining a model of the overall printed board by compiling the power supply networks regarding the plurality of second unit areas; and
solving a circuit Equation by combining the model of the overall semiconductor integrated circuit and the model of the overall printed board.
In accordance with this method of analyzing power supply noise, the power supply is analyzed by combining the model for analyzing power supply noise of the semiconductor integrated circuit and the model for analyzing power supply noise of the printed board. As a result, with regard to the semiconductor integrated circuit of interest, the influence of power supply noise generated by another semiconductor integrated circuit on the printed board can be taken into consideration and it is possible to analyze power supply noise that is generated by the semiconductor integrated circuit and propagates along the printed board.
[Patent Document 1]
    JP Patent Kokai Publication No. JP-P2005-251223A[Patent Document 2]    JP Patent Kokai Publication No. JP-P2005-31850A
The entire disclosures of Patent Documents 1 and 2 are incorporated herein by reference thereto. The following analyses are given by the present invention.
The related technology (for example, Patent Document 1) relies solely upon the characteristics of a printed board and bypass condenser (bypass capacitor) and does not take into account the behavior of the LSI chip that is the source of noise. As a result, even if the amount of noise produced by the LSI chip is small, measures for dealing with the power supply noise are taken as an inevitable consequence and there are instances where this leads to excessive quality, i.e., an increase in cost.
An increase in the speed of a semiconductor device causes an increase in power supply noise, and a reduction in voltage causes a reduction in the immunity to power supply noise. This makes it difficult to design the printed board.
Thus, although it has become essential to suppress power supply noise in a printed board, Patent Document 1 does not clearly set forth a method of precisely analyzing power supply noise.
On the other hand, the other related technology (Patent Document 2) makes it possible to take into account the influence of power supply noise generated by another semiconductor integrated circuit on a printed board and to analyze power supply noise that is generated by a semiconductor integrated circuit and propagates along the printed board. However, the invention of Patent Document 2 solves a circuit Equation by combining models of the overall semiconductor integrated circuits and the model of the overall printed board.
In this way, the abovementioned related technology is completely different from design validity verification technology of the present invention, as described below.